Field of the Invention
The present invention generally relates to error-correcting coding using a class of LDPC codes. In particular, the present invention relates to CC-QC-LDPC codes formed by cyclically coupling plural sub-codes, each being a QC-LDPC code, with an advantage of low decoder complexity while achieving an error performance comparable to an LDPCCC.
Description of Related Art
Development of more superior FEC methods is inevitable in the advancement of communication technologies. In the spectrum of limit-approaching techniques, LDPC codes form a promising and interesting candidate that has been proved over the years. It is also noticed that LDPC codes are adopted in more and more digital communication systems.
Plenty of LDPC decoders were proposed, resulting in various implementation achievements. A decoder for a 9216-bit 1/2-rate code was implemented onto an FPGA and its partially parallel architecture achieved a 54 Mbps throughput. Another design used an 8176-bit code and extended the throughput towards 175 Mbps at a 193 MHz clock rate. Thereafter, a design with a 4.7 Gbps throughput, though not really implemented, was even proposed while the code length was thousands of bits. Usually, an LDPC block code cannot be very long; otherwise the decoder complexity becomes very high. As a result, it limits the error performance of LDPC block codes in the waterfall region and produces an error floor that occurs in the high signal-to-noise region. LDPCCCs, compared to LDPC block codes, have better error performance in the waterfall region and are very effective in lowering the error floor. A comparison between LDPC block codes and LDPCCCs is given by COSTELLO, D. J. Jr., et al., “A Comparison Between LDPC Block and Convolutional Codes,” Proceedings of Information Theory and Applications Workshop, San Diego, Calif., USA, Feb. 6-10, 2006, the disclosure of which is incorporated by reference herein in its entirety. An overview of LDPCCCs is also given by COSTELLO et al. Theoretically, LDPCCCs have an infinite length. Yet, the decoder is required to handle and process only one data segment at a time. By keeping the parity-check information in memory, decoding can be performed in a continual manner. Though the LDPCCC decoder is not very complex, it requires a significantly larger amount of storage when compared to an LDPC block decoder. Moreover, the storage space increases linearly with the number of decoding iterations.
It is advantageous if one can design an LDPC code having a long code length so as to achieve a performance comparable to an LDPCCC but a corresponding decoder of this LDPC code can be implemented with a complexity lower than that of the LDPCCC. There is a need in the art for this LDPC code.